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Repository Created on November 18, 2014, 8:50 pm
VUnit is a unit testing framework for VHDL/SystemVerilog
Last updated on November 24, 2022, 2:29 pm
Repository Created on November 8, 2019, 12:08 am
Last updated on September 26, 2020, 1:30 am
Repository Created on November 18, 2015, 6:39 pm
VHDL 1766 310
VHDL 2008/93/87 simulator
Last updated on November 26, 2022, 6:07 pm
Repository Created on September 22, 2016, 12:11 pm
Phoenix Network-On-Chip
Last updated on October 24, 2016, 2:31 pm
Repository Created on August 8, 2016, 7:02 am
MEGA65 FPGA core
Last updated on November 18, 2022, 10:59 am
Repository Created on June 23, 2020, 3:29 pm
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Last updated on November 28, 2022, 12:47 pm
Repository Created on May 11, 2020, 4:30 pm
Framework for emulation of non volatile memory using off-the-shelf FPGAs
Last updated on July 8, 2022, 2:00 am
Repository Created on April 28, 2016, 11:30 am
All the files for ZX-Uno project repository
Last updated on November 3, 2022, 8:16 am
Repository Created on August 11, 2017, 8:52 am
A VHDL-Library for reading a SD-Card with a FPGA in a small test project
Last updated on October 7, 2021, 4:13 pm
Repository Created on July 28, 2015, 3:00 pm
A plain VHDL implementation of a small microprocessor fully compatible with the ISA of the well known PicoBlaze by Ken Chapman.
Last updated on June 30, 2022, 12:34 pm
Repository Created on August 26, 2016, 5:57 pm
Develop the directors structure and testing infrastructure for CoreLib
Last updated on March 11, 2019, 10:16 pm
Repository Created on July 20, 2019, 3:44 pm
Last updated on September 26, 2022, 8:31 am
Repository Created on February 6, 2019, 12:58 pm
Efficient Multiplication in Finite Field Extensions of Degree 5
Last updated on March 28, 2019, 2:41 pm
Repository Created on April 10, 2014, 4:54 pm
Computer Architecture Final Project
Last updated on August 17, 2017, 10:30 am
Repository Created on February 22, 2018, 7:08 pm
This is for the group CPTR 380 Computer Architecture class project
Last updated on March 16, 2022, 12:31 am
Repository Created on October 27, 2014, 11:14 am
Last updated on October 3, 2016, 8:06 am
Repository Created on February 15, 2018, 1:14 am
A robot that is like the RC Jumper in Watch Dogs 2 (THIS REPO has been MOVED)
Last updated on August 8, 2019, 3:03 pm
Repository Created on December 16, 2014, 2:21 pm
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Last updated on November 23, 2022, 8:19 am
Repository Created on January 30, 2016, 3:36 pm
Hostmot2 FPGA code for SoC/FPGA platforms from Altera and Xilinx
Last updated on September 18, 2022, 8:32 pm
Repository Created on May 10, 2017, 9:03 pm
Last updated on May 17, 2017, 1:22 pm
Repository Created on November 27, 2017, 4:32 pm
Collections of all lecture note, lab, tutorial and etc for First Year and Second Year
Last updated on October 26, 2022, 7:40 am
Repository Created on November 8, 2018, 4:43 am
Last updated on November 26, 2022, 4:18 am
Repository Created on May 15, 2016, 4:38 pm
Implementation of a Neural Network for the XOR problem as part of project work for Digital System Design course .
Last updated on November 16, 2016, 2:24 pm
Repository Created on August 11, 2016, 10:27 am
Yet another CDEC, CDEC Voyager : Very simple 8-bit architecture CPU for computer architecture education
Last updated on May 25, 2018, 9:22 am
Repository Created on November 8, 2011, 12:11 am
Last updated on June 9, 2022, 12:20 am
Repository Created on January 9, 2017, 3:44 pm
Library of utilities such as cores, procedures and functions, commonly shared between FPGA projects.
Last updated on August 15, 2022, 11:21 am
Repository Created on November 10, 2016, 5:48 am
Last updated on November 10, 2016, 11:42 am
Repository Created on July 10, 2009, 7:11 pm
Pong for Spartan3 FPGA-Board written in VHDL
Last updated on August 23, 2021, 12:47 am
Repository Created on May 4, 2010, 7:31 pm
A simple brainfuck processor implemented in VHDL.
Last updated on January 3, 2021, 1:19 am
Repository Created on March 17, 2012, 6:14 am
Processors are cool.
Last updated on July 29, 2017, 3:12 am