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Repository Created on February 2, 2018, 7:49 pm
Micro CPU
Last updated on February 2, 2018, 8:19 pm
Repository Created on August 16, 2019, 6:59 am
Support files for participating in a Fomu workshop
Last updated on November 18, 2022, 7:20 am
Repository Created on September 26, 2017, 12:08 am
Verilog 1386 506
RTL, Cmodel, and testbench for NVDLA
Last updated on November 29, 2022, 7:19 am
Repository Created on September 2, 2015, 4:01 am
CDECをDE0上に実装するプロジェクト
Last updated on December 11, 2015, 2:44 am
Repository Created on January 17, 2018, 6:03 pm
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
Last updated on November 5, 2022, 3:24 am
Repository Created on December 12, 2018, 6:35 am
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Repository Created on September 7, 2015, 8:45 am
Small footprint and configurable PCIe core
Last updated on November 30, 2022, 9:43 am
Repository Created on April 8, 2018, 4:19 pm
Human Resource Machine - CPU Design #HRM
Last updated on October 7, 2022, 5:13 am
Repository Created on June 3, 2018, 7:00 pm
Simple 8-bit UART realization on Verilog HDL.
Last updated on November 9, 2022, 9:51 am
Repository Created on October 28, 2019, 5:48 pm
OpenROAD's unified application implementing an RTL-to-GDS Flow
Last updated on December 1, 2022, 4:16 am
Repository Created on April 5, 2021, 3:14 pm
https://caravel-user-project.readthedocs.io
Last updated on November 22, 2022, 5:19 am
Repository Created on November 14, 2019, 3:23 pm
Snake Game for Basys3 FPGA
Last updated on December 14, 2019, 4:45 am
Repository Created on August 22, 2019, 6:02 am
A tiny Open POWER ISA softcore written in VHDL 2008
Last updated on November 24, 2022, 8:39 pm
Repository Created on April 16, 2018, 7:49 pm
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
Last updated on September 15, 2022, 9:54 am
Repository Created on July 5, 2018, 6:39 pm
Single pipeline AES 128 bit encryption using S-box as Look up table.
Last updated on February 27, 2022, 7:05 am
Repository Created on May 18, 2020, 6:50 pm
Last updated on June 2, 2020, 11:35 am
Repository Created on October 18, 2018, 9:27 am
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
Last updated on November 15, 2022, 8:00 pm
Repository Created on May 8, 2014, 10:47 pm
A library of FPGA designs and re-usable modules for I/O and internal connectivity in SpiNNaker systems.
Last updated on February 16, 2022, 10:11 am
Repository Created on January 9, 2017, 4:43 am
:fireworks: PEW PEW Project
Last updated on July 2, 2022, 11:34 pm
Repository Created on October 13, 2020, 2:43 pm
Proyecto desarrollo chip RISC-V en tecnología STMicroelectronics
Last updated on June 9, 2022, 8:54 pm
Repository Created on April 25, 2016, 11:30 am
SSAMAI Multicycle CPU
Last updated on May 2, 2018, 7:10 am
Repository Created on October 17, 2014, 6:42 am
This is a myhdl test environment for the open-cores jpeg_encoder.
Last updated on July 3, 2022, 10:28 am
Repository Created on October 6, 2017, 5:00 pm
Laboratorio Integrado IV
Last updated on August 17, 2019, 7:25 pm
Repository Created on September 6, 2016, 9:40 pm
A custom 16-bit computer
Last updated on July 24, 2022, 9:43 pm
Repository Created on February 7, 2022, 12:20 pm
Last updated on September 10, 2022, 11:53 am
Repository Created on July 14, 2016, 10:45 pm
Reference HDL code for the MATRIX Creator's Spartan 6 FPGA
Last updated on November 11, 2022, 12:43 pm
Repository Created on December 4, 2020, 10:11 pm
A collection of formal properties for hardware buses, and cores using them.
Last updated on February 12, 2021, 9:20 pm
Repository Created on September 22, 2022, 7:16 pm
Cofección de un circuito decodificador de Gray
Last updated on October 11, 2022, 6:20 am
Repository Created on August 25, 2020, 1:35 pm
Fabric generator and CAD tools
Last updated on November 28, 2022, 8:11 pm