💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.

CoreFreq is a CPU monitoring software designed for the 64-bits Processors.

SST Architectural Simulation Components and Libraries

A graphical processor simulator and assembly editor for the RISC-V ISA

An imaginary 16-bit CPU architecture with custom assembly language and instructions

Intel® Performance Counter Monitor (Intel® PCM)

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

Implementation of the processor model

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

A processor cache simulator for the MIPS architecture

Introduction to computer system abstractions reflected in programming languages, operating systems, architectures, and networks. Topics include: overview of computer and processor architecture, instruction set architecture and introduction to assembly language, C programming, system calls, processes and process memory layout, interfaces for memory

Projects of the computer architecture lab (Spring 02) at the University of Tehran.

Logisim implementation of a 16-bit single cycle and pipelined RISC processor designed from an instruction set.

A RISC custom-ISA, 16-Bit Processor

Лабораторные работы и учебные материалы по курсу ОПД, ИТМО ИВТ

RISC-V assembly code I wrote as part of my COAL course at UIT University.

:computer: This course is about computer science basics.

ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.

A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

A Pipelined RISC-V Processor with forwarding support and hazard detection.

Senior Design Project at UW-Madison ECE

RISC22 is a simple 22-bit RISC CPU designed in VHDL, featuring a minimal instruction set and a pipelined architecture for efficient execution.

8-bit Processor emulator designed and impemented using Java SE

[under progress] A functional processor in Verilog which supports the Y86-64 ISA with pipelining with hazard control.

RISC-V RV32I CPU core in SystemVerilog

A Python model for a RISC-V Single Cycle Processor and simple Assembler

Collection of Lab assignments in a Computer Architecture course.

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.