Problem 1: device tree mismatch in embeddedsw The rfdc driver expects a device tree with most of the configuration tucked into a "param-list" entry, as can be seen here: Status = metal_linux_get_device_property(DevicePtr, XRFDC_CONFIG_DATA_PROPERTY, &Data, XRFDC_DEVICE_ID_SIZE); However...

In xfsbl_debug.h, line 70 https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_apps/zynqmp_fsbl/src/xfsbl_debug.h#L70 : #define XFsbl_Printf(DebugType,...) \ if(((DebugType) & XFsblDbgCurrentTypes)!=XFSBL_SUCCESS) {xil_printf (__VA_ARGS__); } XFSBL_SUCCESS is defined in xfsbl_error.h but i...

Please re-test the example found here: https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c. It doesn't work, and I'm not the first to notice: https://forum.digilent.com/topic/24684-zynq-ultrascale-example-with-freertos-using-interrupts-o...

In PG210 V4.1, it is mentioned that USER_REG_0 address has been updated from 0x0184 to 0x0134 starting from v2.3, but it is still at 0x0184 in file 'xxxvethernet_hw.h' on master branch. USER_REG_1 is also still present although it has been removed in v2.3. File 'xxxvethernet_hw.h', lines 74 and 75:...

The handler with XUARTPS_EVENT_RECV_ORERR set to the event never occurs. The only way to detect receive overrun is from XUARTPS_EVENT_RECV_ERROR, would be to read last errors as in the comment in code but it's also not implemented.

I'm trying to get UART16550 (xuartns550 driver) to receive packets of unknown length (Modbus RTU). My idea was to use XUartNs550_Recv, set the buffer length to the maximum possible size of Modbus message and wait for the timeout event. Unfortunately, a timeout event occurs every time after the FIFO...

I'm experiencing issue when transmitting reasonable amount of data using interrupt driven UART. In general it is working but sometimes (sporadically) it looks like missing final UART interrupt (I guess XUARTPS_IXR_TXEMPTY) when sending last chunk. Therefore I never get XUARTPS_EVENT_SENT_DATA even...

Bug injected in commit: a4acb9e Hi, During a project update, we have observe major drop of data on a master AXI QSPI IP (single lane) due to an incomplete fix in version 4.7 of XSpi driver in the interrupt handler. The previous version had a bug leading to an overrun of receive FIFO, but the fix is...

I am a bit confused about the functions to use to read and write from ONFI flash memory. Do I use the xnandps_onfi.c or the xnandps.c to read and write from ONFI flash memory? I see that xpandps is bein used in onfi.c as well so am a bit confused.