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According to the comment:
embeddedsw/XilinxProcessorIPLib/drivers/uartps/examples/xuartps_intr_example.c
Line 247
in
b9b64f5
* The setting of 8 will timeout after 8 x 4 = 32 character times....
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In this function, the second of these two assigns is wrong:
Status->FrameInitTrigger =
XDfePrach_RdBitField(XDFEPRACH_FRAME_INIT_TRIGGERED_WIDTH,
XDFEPRACH_FRAME_INIT_TRIGGERED_OFFSET,
Val);
Status->FrameInitTrigger = XDfePrach_RdBitField(
XDFEPRACH_FRAME_ERROR_WIDTH, XDFEPRA...
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I'm seeing the folowing build errors when I try to rebuild pmu firmware (either from xsct, manually or yocto).
The hardware in use is zu11eg.
mb-gcc -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mxl-soft-mul -mcpu=v9.2 -MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -...
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This code:
https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/data/freertos10_xilinx.tcl#L885-L889
sets portTICK_TYPE_IS_ATOMIC for psu_cortexr5 but I'm at a loss for why it does this?
The way things are now, calling xTaskGetTickCounter takes about 260 CPU cycles, wher...
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When the ByteCount is the multiple of the sector size, the sector_cnt is miscalculated.
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Currently, the spips driver, in both the XSpiPs_PolledTransfer and XSpiPs_Transfer calls XSpiPs_Enable() AFTER setting the chip select. It should call XSpiPs_Enable BEFORE setting the chip select.
Calling XSpiPs_Enable causes SCLK to goto the polarity determined by CPOL and this needs to happen BEFO...
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in file ThirdParty/bsp/freertos10_xilinx/src/Source/portable/GCC/ARM_CA9/portmacro.h and other ports
/* Called at the end of an ISR that can cause a context switch. */
#define portEND_SWITCHING_ISR( xSwitchRequired )\
{ \
extern uint32_t ulPortYieldRequired; \
\
if( xSwitch...
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https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/usb/src/xusb_endpoint.c#L474
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/usb/src/xusb_endpoint.c#L527
I believe this code is designed to overcome AXI latency by converting byte transfers i...
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I’m using a very simple baremetal Zynq lwIP based UDP echo server
https://github.com/dnygren/zynq_echo_servers_udp/tree/master/C%2B%2B/zynq_echo_server_udp_cpp/src
to test lwIP's UDP functionality. It is built using Xilinx Vivado/SDK 2018.3, standalone 6.8, along with lwIP 2.11 v1.7 on a PicoZed boa...
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Hi all,
currently, the XilSKey_ZynqMp_EfusePs_Write function calls:
XilSKey_Efuse_ConvertBitsToBytes(InstancePtr->Ppk0Hash, Ppk0InBits, XSK_ZYNQMP_EFUSEPS_PPK_SHA3HASH_LEN_IN_BITS);
That means it interprets InstancePtr->Ppk0Hash as bits and writes bytes into the Ppk0InBits array. Shouldn't it...